Cost-effective hardware sharing architectures of fast 8x8 and 4x4 integer transforms for H.264/AVC

In this paper, the novel hardware sharing architectures are proposed for realizations of fast 4x4 and 8x8 forward / inverse integer transforms in the H.264/AVC. Based on matrix factorizations, the cost-effective architectures for fast one-dimensional (1-D) 4x4 and 8x8 forward / inverse integer transforms can be derived through the Kronecker and direct sum operations. By applying the concept of hardware sharing, the proposed hardware schemes for fast integer transforms need less number of shifters and adders than the direct realization architecture, where the direct architecture just implements the individual 4x4 and individual W integer transforms independently. With low hardware cost and regular modularity, the proposed hardware sharing architectures are suitable for VLSI implementations to accomplish the H.264/AVC signal processing.