Strained-Si channel heterojunction p-MOSFETS

被引：24
|
作者：
Armstrong, GA [1 ]
Maiti, CK [1 ]
机构：
[1] Queens Univ Belfast, Dept Elect & Elect Engn, Belfast BT9 5AH, Antrim, North Ireland
来源：
SOLID-STATE ELECTRONICS | 1998年 / 42卷 / 04期
关键词：
D O I：
10.1016/S0038-1101(98)00060-4
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A simulation study of a short-channel strained-Si p-MOSFET is presented. An analytical model for hole mobility enhancement in strained silicon has been used in a two-dimensional (2D) device simulator to evaluate the strain dependence of the drain current and transconductance. Simulation results have been verified with experimental device results and the leverage of the strained-Si channel p-MOSFET over conventional Si p-MOSFETs is shown both at low temperature and room temperature. Optimal confinement of holes within the strained silicon occurs for a graded Si0.7Ge0.3 buffer cap thickness of 40 nm. This layer structure gives rise to an enhancement in transconductance of up to 60%. (C) 1998 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码：487 / 498
页数：12
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