PIPELINE IMPLEMENTATION OF THE 128-BIT BLOCK CIPHER CLEFIA IN FPGA

被引：9

作者：

Kryjak, Tomasz ^{[1
]}

Gorgon, Marek ^{[1
]}

机构：

[1] AGH Univ Sci & Technol, Dept Automat, Krakow, Poland

来源：

FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS | 2009年

关键词：

D O I：

10.1109/FPL.2009.5272264

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

The article presents a pipeline implementation of the block cipher CLEFIA. The article examines three known methods of implementing a single encryption round and proposes a new fourth method. The article proposes the implementation of a key scheduler, which is highly compatible with pipeline encryption. The article contains a detailed analysis of the data processing path for the 128-bit key version of the algorithm and verifies its operation on two FPGA cards in practice. On the basis of one of these cards, the article proposes a prototype of an effective supercomputer-compatible hardware accelerator (High Performance Computing Application).

引用

页码：373 / 378

页数：6

共 50 条

[21] 128bit block cipher - CIPHERUNICORN-A
Tsunoo, Yukiyasu
NEC Research and Development, 2002, 43 (03): : 183 - 187
[22] 128bit block cipher 'CIPHERUNICORN-A'
Tsunoo, Yukiyasu, 2000, NEC Creative Ltd., Tokyo, Japan (41):
[23] FPGA Implementation of the "PYRAMIDS" Block Cipher
AlKalbany, A.
Al hassan, H.
Saeb, M.
PROCEEDINGS OF WORLD ACADEMY OF SCIENCE, ENGINEERING AND TECHNOLOGY, VOL 5, 2005, 5 : 267 - 273
[24] FPGA implementation of the "pyramids" block cipher
AlKalbany, A
Al Hassan, HA
Saeb, M
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2005, : 271 - 275
[25] 128bit block cipher - CIPHERUNICORN-A
Tsunoo, Y
NEC RESEARCH & DEVELOPMENT, 2002, 43 (03): : 183 - 187
[26] 128bit block cipher "CIPHERUNICORN-A"
Tsunoo, Y
NEC RESEARCH & DEVELOPMENT, 2000, 41 (04): : 322 - 326
[27] VLSI architecture of burst mode acceleration for 128-bit block ciphers
Mitsuyama, Y
Andales, Z
Onoye, T
Shirakawa, I
Arungsrisangchai, I
2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, PROCEEDINGS, 2002, : 344 - 347
[28] Unified hardware architecture for 128-bit block ciphers AES and Camellia
Satoh, A
Morioka, S
CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS CHES 2003, PROCEEDINGS, 2003, 2779 : 304 - 318
[29] Burst mode: A new acceleration mode for 128-bit block ciphers
Mitsuyama, Y
Andales, Z
Onoye, T
Shirakawa, I
PROCEEDINGS OF THE IEEE 2002 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2002, : 151 - 154
[30] FPGA-based 128-bit Chaotic Encryption Method for Voice Communication
Riyadi, Munawar A.
Pandapotan, Natanael
Khafid, M. Reza A.
Prakoso, Teguh
2018 INTERNATIONAL SYMPOSIUM ON ELECTRONICS AND SMART DEVICES (ISESD 2018): SMART DEVICES FOR BIG DATA ANALYTIC AND MACHINE LEARNING, 2018, : 34 - 38

← 1 2 3 4 5 →