High-speed low-complexity implementation for data weighted averaging algorithm

被引：0
|
作者：
Lee, DH [1 ]
Li, CC [1 ]
Kuo, TH [1 ]
机构：
[1] Natl Cheng Kung Univ, Dept Elect Engn, Tainan 70101, Taiwan
来源：
2002 IEEE ASIA-PACIFIC CONFERENCE ON ASIC PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, a high-speed, low-complexity implementation for Data Weighted Averaging (DWA) algorithm is presented. Different from other published implementations, the maximum speed-limited function of the DWA algorithm, decoding for control signal generation and adding for register value updating, are replaced by carry look-ahead and rotating. Additionally, register simplification is adopted to reduce area costs. This design for a 3-bits 8-elements example can operate at a 800MHz clock rates for post-layout simulations, and costs only 254 transistors.
引用
收藏
页码：283 / 286
页数：4
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