Distributed BIST architecture to combat delay faults

被引：1

作者：

Savir, J ^{[1
]}

机构：

[1] New Jersey Inst Technol, Dept Elect & Comp Engn, Newark, NJ 07102 USA

来源：

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 2000年 / 16卷 / 04期

关键词：

LSSD; SRL; BIST; LFSR; MISR; delay test;

D O I：

10.1023/A:1008370019685

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

To successfully combat delay faults there is an urgent need for a proper design for testability (DFT). The foundation of any DFT methodology rests on its scan design. This paper describes three versions of a new design of a shift register latch that lend themselves to distributed self-test and delay test. The advantages of this new SRL is faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Adoption of this new DFT methodology brings us closer to the ideal target of one test-per-clock as opposed to one test-per-scan. Operation, cost, and other attributes are studied in detail. Results of adopting one of these SRLs are reported on ten pilot chips.

引用

页码：369 / 380

页数：12

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