BIST of delay faults in the logic architecture of symmetrical FPGAs

被引：7

作者：

Girard, P ^{[1
]}

Héron, O ^{[1
]}

Pravossoudovitch, S ^{[1
]}

Renovell, M ^{[1
]}

机构：

[1] Univ Montpellier 2, CNRS, UMR 5506, Lab Informat Robot & Microelect Montpellier, F-34392 Montpellier 05, France

来源：

10TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/OLT.2004.1319686

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we propose a BIST scheme for exhaustive testing all delay faults in the logic architecture of symmetrical FPGAs. This scheme is applicable in a Manufacturing-Oriented Test (MOT) context. Our technique enables the detection of delay faults in the logic architecture and consists in chaining the logic cells in a specific way. The test of all the delay faults can be done with a reduced test sequence and does not require expensive ATE. To illustrate its feasibility, this BIST approach has been implemented in a VIRTEX FPGA from XILINX Inc.

引用

页码：187 / 192

页数：6

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