A HIGH-PERFORMANCE ARCHITECTURE OF JPEG2000 ENCODER

This article presents hardware architecture of JPEG2000 encoder core, oriented for HD video broadcast and surveillance applications. Thanks to developed efficient 2-D DWT engine that is capable of computing four coefficients per clock cycle, and adopted two EBCOT TIER-1 modules, with smart switching of the channels, the maximum compression speed of 180 Msamples/s at 100 MHz, in lossy mode is achieved. The architecture is implemented in VHDL and synthesised for FPGA devices, and ASIC 0.13 pm CMOS technology. Performance simulations, conducted on a set of natural images and video sequences, have revealed that the encoder is capable of processing 1080p 4:4:4 signal with a speed of 30 frames per second. Additionally, an excellent quality of reconstructed images has been observed, with respect to the reference, software encoder.