Influence of Design Considerations on Hot Carrier Injection Degradation of STI-based LDMOS Transistors

In this paper, the influence of design parameters on hot carrier injection (HCI) degradation of shallow trench isolation (STI) based n-channel laterally diffused metal-oxide-semiconductor (n-LDMOS) transistors using TCAD simulation was analyzed. The design parameters involved in this study were STI depth, gate oxide thickness as well as p-substrate doping concentration simulated based on the stress-measure testing technique. The effect on the device parameters such as on-resistance (Ron), impact ionization rate, and interface traps concentration had been investigated and explained in detail. From the results obtained, it is found that larger STI depth and larger gate oxide thickness shows lower HCI effect. The Ron degradation is observed to reduce by 52.2% and 79.76% when the STI depth is increased to 0.3 mu m and 0.4 mu m respectively for 10ks stress time. It is also observed that higher p-substrate doping concentration exhibits higher HCI degradation.