Cellular Automata Based Hardware Accelerator for Parallel Maze Routing

被引：0

作者：

Saurabh, Shashank ^{[1
]}

Lin, Kuen-Wey ^{[2
]}

Li, Yih-Lang ^{[2
]}

机构：

[1] IIT BHU, Dept Elect Engn, Varanasi 221005, Uttar Pradesh, India

[2] Natl Chiao Tung Univ, Inst Comp Sci & Engn, Hsinchu 300, Taiwan

来源：

PROCEEDINGS OF THE IEEE INTERNATIONAL CONFERENCE ON ADVANCED MATERIALS FOR SCIENCE AND ENGINEERING (IEEE-ICAMSE 2016) | 2016年

关键词：

maze routing; hardware accelerator; cellular automata;

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

This paper introduces a scalable hardware design to accelerate the maze algorithm for VLSI routing on Cellular automata (CA). The time-complexities of wave-propagation and back-tracing on CA are both O(n) while constant time for label clearing. Innately high parallelism of CA largely reduces the runtime in wave propagation and label clearing. The RTL implementation for this design has been developed in Verilog and a cell lattice of 35. 35 cells has been implemented on FPGA. The runtime of the proposed CA is shorter than that on a sequential computer by about four to five orders of magnitude.

引用

页码：680 / 683

页数：4

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