Design and Test of a Low-Power 90nm Xor/Xnor Gate for Cryptographic Applications

被引：0

作者：

Tena-Sanchez, Erica ^{[1
,2
]}

Castro, Javier ^{[3
]}

Acosta, Antonio J. ^{[1
,2
]}

机构：

[1] Univ Seville, Seville, Spain

[2] Inst Microelect Sevilla, IMSE CNM CSIC, Seville, Spain

[3] Anafocus Co, Seville, Spain

来源：

2014 24TH INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS) | 2014年

关键词：

PRE-CHARGE LOGIC; DPA-RESISTANCE; PERFORMANCE;

D O I：

暂无

中图分类号：

TE [石油、天然气工业]; TK [能源与动力工程];

学科分类号：

0807 ; 0820 ;

摘要：

In this paper, the design of a XOR/XNOR gate for low-power cryptographic applications is presented. The proposed gate optimizes the SABL (Sense Amplifier Based Logic) gate, widely used in cryptocircuit implementations, by removing residual charge in the pull-down circuit and simplifying the pull-up. The resulting gate improves SABL in terms of area, power consumption, propagation delay and resilience against Differential Power Analysis (DPA) attacks. To demonstrate the gain in performances, both gates have been designed, physically implemented and experimentally characterized, in a 90nm TSMC technology. Experimental results show a reduction of 15% in area, 12% in power consumption, and 40% in delay in the proposed gate. To demonstrate the gain in security of the proposal, simulation-based DPA attacks have been performed on respective Kasumi Sbox9 implementations, being our proposal suitable for inmediate application in high-performance secure cryptographic applications.

引用

页数：8

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