A Heterogeneous Integration Management for Semiconductor Package

The 5th Generation wireless systems popularity will push the package development into a high performance and heterogeneous integration form Packaging process further developed it in a larger area and higher integration complexity for future 5G connectivity devices application. For high I/O density and high performance packages, the promising Fan Out Chip on Substrate provides a solution to match Outsourced Semiconductor Assembly and Testing capability. In this paper, to reduce the panel warpage effect, we used three dimensional finite element method and advanced Metrology Analyzer to find the optimum thickness and Coefficient of Thermal Expansion about the glass carrier. Regarding FOCoS device, packages with 9 complex chips especially with fine line RDL and multi-size mu bump joint structures inside have been successfully developed In reliability examination, the test vehicle also passed the JEDEC qualification, respectively.