High performance polyphase FIR filter structures in VHDL language for Software Defined Radio based on FPGA

Digital filters are necessary in digital transmitter / receiver side and popularity of Software Defined Radio (SDR) is forcing complex digital signal processing blocks to be implemented in parallel design flow on FPGA or ASIC. The goal of this paper is to develop efficient pipelined polyphase FIR filter structures in VHDL language for RTL synthesis on FPGA. The proposed structures contain fully parallel polyphase decimation and interpolation FIR filter models. The first part of this paper is focused on formulation of distributed arithmetic technique with polyphase decomposition, which represents the core of designed models. The second part describes mentioned polyphase FIR VHDL models. The extensive emphasis will be put on efficient pipelined implementation with excellent registered performance and optimal design size balance. The third part of this paper deals with rapid design and simulation of proposed VHDL models. The result of RTL synthesis is finally discussed. Very good performance and optimal design size are main benefits of proposed polyphase FIR filters. Developed structures are very suitable for multichannel operation in digital I/Q receiver.