A 12-b 4-MS/s SAR ADC With Configurable Redundancy in 28-nm CMOS Technology

A charge redistribution successive-approximation-register analog-to-digital converter (ADC) with nonbinary redundant search tree is presented. The combination of thermometer-coded and series-split binary-weighted capacitive digital to analog converters is area efficient and enables high resolution in a standard digital process without high matching requirements. A power and timing-effective latch-based implementation of the digital conversion control is introduced. Fabricated in 28-nm CMOS, the ADC achieves an effective number of bits of 10.1 b and consumes 115 mu W at a conversion rate of 4-MS/s. Measurement results offer a direct comparison of attainable speed at different redundancy settings.