How to transform an architectural synthesis tool for Low Power VLSI designs

High Level Synthesis (HLS) for Low Power VLSI design is a complex optimization problem due to the Area/Time/Power interdependence. As few low power design tools are available, a new approach providing a modular low power synthesis method is proposed. Although based for the moment on a generic architectural synthesis tool Gaut, the use of different "commercial" tools is possible. The Gaut_w HLS tool is constituted of low power modules : High level power dissipation estimation, Assignment, Module selection (operators and supply voltage), Optimization criteria and Operators library. As illustration, power saving factors on DWT algorithms are presented.