Low power test application with selective compaction in VLSI designs

被引：0

作者：

Czysz, D. ^{[1
]}

Rajski, J. ^{[1
]}

Tyszer, J. ^{[2
]}

机构：

[1] Mentor Graph Corp, Wilsonville, OR 97070 USA

[2] Pozna Univ Technol, Poznan, Poland

来源：

PROCEEDINGS INTERNATIONAL TEST CONFERENCE 2012 | 2012年

关键词：

RESPONSE COMPACTION; COMPRESSION; MINIMIZATION; UNKNOWNS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The paper presents an extended summary of the PhD thesis that tackles a low power decompression of test cubes in EDT environment and compaction of test responses in the presence of unknown states. The proposed low power decompression schemes allow one to reduce the load and unload switching activity by more than 93% and capture transitions by 52%. The X-masking scheme introduced in the thesis offers up to 48,000x compression of control data, and eliminates all unknown states from test responses.

引用

页数：10

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