On-chip triple-error correction and quadruple-error detection ECC structure for ultra-large, single-chip memories

被引：5

作者：

Alzahrani, FM ^{[1
]}

Chen, T ^{[1
]}

机构：

[1] Colorado State Univ, Dept Elect Engn, Ft Collins, CO 80523 USA

来源：

COMPUTERS & ELECTRICAL ENGINEERING | 2000年 / 26卷 / 05期

关键词：

error correction codes (ECCs); memory; CMOS logic; VLSI; reliability;

D O I：

10.1016/S0045-7906(99)00034-8

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Soft errors resulting from alpha-particle strikes are one of the major factors that reduces the reliability of memory chips. One way to improve reliability of memory chips is to employ an on-chip error-correcting code (ECC) structure. This paper presents a triple-error correcting and quadruple-error detecting (TEC-QED) code, that is capable of correcting three and detecting four soft errors, simultaneously. The TEC-QED code design is based on odd-weight-column SEC-DED code in conjunction with the parity technique. Results show that timing overhead of less than 11 ns can be expected. The proposed code improves the mean time between failure (MTBF) by a factor of 210%, when compared to DEC APC, and by a factor of 31%, when compared to the interleaved SEC code. (C) 2000 Elsevier Science Ltd. All rights reserved.

引用

页码：317 / 335

页数：19

共 9 条

[1] A Unified Framework for Error Correction in On-Chip Memories
Sala, Frederic
Duwe, Henry
Dolecek, Lara
Kumar, Rakesh
[J]. 2016 46TH ANNUAL IEEE/IFIP INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEMS AND NETWORKS WORKSHOPS (DSN-W), 2016, : 268 - 274
[2] Correction Prediction: Reducing Error Correction Latency for On-Chip Memories
Duwe, Henry
Jian, Xun
Kumar, Rakesh
[J]. 2015 IEEE 21ST INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA), 2015, : 463 - 475
[3] THE RELIABILITY OF SEMICONDUCTOR RAM MEMORIES WITH ON-CHIP ERROR-CORRECTION CODING
GOODMAN, RM
SAYANO, M
[J]. IEEE TRANSACTIONS ON INFORMATION THEORY, 1991, 37 (03) : 884 - 896
[4] Timing error correction techniques for voltage-scalable on-chip memories
Karl, E
Sylvester, D
Blaauw, D
[J]. 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 3563 - 3566
[5] Design of on-chip error correction systems for multilevel NOR and NAND flash memories
Sun, F.
Devarajan, S.
Rose, K.
Zhang, T.
[J]. IET CIRCUITS DEVICES & SYSTEMS, 2007, 1 (03) : 241 - 249
[6] SINGLE-EVENT UPSET (SEU) IN A DRAM WITH ON-CHIP ERROR CORRECTION
ZOUTENDYK, JA
SCHWARTZ, HR
WATSON, RK
HASNAIN, Z
NEVILL, LR
[J]. IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1987, 34 (06) : 1310 - 1315
[7] A review of on-chip timing error detection/correction methods for logic pipeline
Kim, Jae-Joon
[J]. 2015 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2015, : 89 - 90
[8] SINGLE-EVENT UPSET (SEU) IN A DRAM WITH ON-CHIP ERROR CORRECTION.
Zoutendyk, J.A.
Schwartz, H.R.
Watson, R.K.
Hasnain, Z.
Nevile, L.R.
[J]. IEEE Transactions on Nuclear Science, 1987, NS-34 (06)
[9] A Near-Threshold-Voltage Network-on-Chip with a Metastability Error Detection and Correction Technique for Supporting a Quad-Voltage/Frequency-Domain Ultra-Low-Power System-on-a-Chip
Lin, Chuxiong
He, Weifeng
Sun, Yanan
Pei, Bingxi
Mao, Zhigang
Seok, Mingoo
[J]. 2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC), 2020, : 394 - +

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