Efficient on-chip communications for data-flow IPs

被引：2

作者：

Fraboulet, A ^{[1
]}

Risset, T ^{[1
]}

机构：

[1] Inst Natl Sci Appl, Citi, F-69621 Villeurbanne, France

来源：

15TH IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, PROCEEDINGS | 2004年

关键词：

system on chip; SoC simulation; high level synthesis; interface generation;

D O I：

10.1109/ASAP.2004.1342479

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We explain a systematic way of interfacing data-flow hardware accelerators (IP) for their integration in a system on chip. We abstract the communication behaviour of the data flow IP so as to provide basis for an interface generator. We also explain which parameter this interface generator has to take into account. We validate our interface mechanism by a cycle accurate bit accurate simulation of a SoC integrating a data-flow IP.

引用

页码：293 / 303

页数：11

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