A SEU/MBU Tolerant SRAM Bit Cell Based on Multi-Input Gate

被引：0
|
作者：
Zou Sanyong [1 ,2 ]
机构：
[1] NUDT, Dept Elect Sci & Engn, Changsha, Hunan, Peoples R China
[2] China Acad Engn Phys, Inst Elect Engn, Changsha, Hunan, Peoples R China
来源：
2017 4TH INTERNATIONAL CONFERENCE ON ELECTRICAL AND ELECTRONIC ENGINEERING (ICEEE 2017) | 2017年
关键词：
SRAM; NAND2; NOR2; SEU; MBU; DESIGN;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper a new structure of SRAM bit cell is proposed with better stability and insensitivity of cell size. The proposed SRAM cell consists of mUlti-input-gate unit instead of the not-gate compared with the 6T cell. Simulation results show that the proposed cell shares better SEU (Single Event Upset) tolerant and MBU (Multiple Events Upset) tolerant ability than the DICE cell.
引用
收藏
页码：251 / 255
页数：5
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