A compact FD-SOI MOSFETs fabrication process featuring SixGe1-x gate and Damascene-Dummy SAC

被引：2

作者：

Hisamoto, D ^{[1
]}

Kachi, T ^{[1
]}

Tsujikawa, S ^{[1
]}

Miyauchi, T ^{[1
]}

Kusukawa, K ^{[1
]}

Sakuma, N ^{[1
]}

Homma, Y ^{[1
]}

Yokoyama, N ^{[1
]}

Ootsuka, F ^{[1
]}

Onai, T ^{[1
]}

机构：

[1] Hitachi Ltd, Cent Res Lab, Kokubunji, Tokyo 1858601, Japan

来源：

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIT.2000.852828

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A compact FD-SOI CMOS fabrication process and device structure was demonstrated. A new damascene-dummy SAC process enabled to fabricate reliable contacts with ultra-thin SOI layers. We showed that using in-situ-boron-doped SixGe1-x as a gate material, the adequate threshold voltage of FD-SOI was realized.

引用

页码：208 / 209

页数：2

共 2 条

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[J]. ESSDERC 2022 - IEEE 52ND EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), 2022, : 356 - 359
[2] Fabrication of high-density Si and SixGe1-x nanowire arrays based on the single step plasma etching process
Martin, Mickael
Avertin, Sebastien
Chevolleau, Thierry
Dhalluin, Florian
Ollivier, Maelig
Baron, Thierry
Joubert, Olivier
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[J]. JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2013, 31 (04):

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