Effect of Source/Drain Asymmetry on the Performance of Z-RAM® Devices

被引：0

作者：

Mohapatra, N. R. ^{[1
]}

vanBentum, R. ^{[1
]}

Pruefer, E. ^{[1
]}

Maszara, W. P. ^{[1
]}

Caillat, C. ^{[2
]}

Chalupa, Z. ^{[2
]}

Johnson, Z. ^{[2
]}

Fisch, D. ^{[2
]}

机构：

[1] AMD Fab36 LLC & Co KG, Wilschdorfer Landstr 101, D-01109 Dresden, Germany

[2] Innovat Silicon, PSE B, CH-1015 Lausanne, Switzerland

来源：

2009 IEEE INTERNATIONAL SOI CONFERENCE | 2009年

关键词：

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

In this paper, the performance of Zero capacitor RAM (Z-RAM (R)) devices, developed in a 45nm SOI CMOS technology, is compared with both symmetric and asymmetric doping schemes. It is shown that the asymmetrically doped Z-RAM (AD) devices offer much better memory performance compared to the symmetrically doped Z-RAM (SD) devices.

引用

页码：39 / +

页数：2

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