Horizontal Vertical and SuperQueen Parity (HVSQ) Method for Soft Error Tolerance

被引：0

作者：

Raju, S. M. Taslim Uddin ^{[1
]}

Rahman, Md Shamimur ^{[1
]}

机构：

[1] Khulna Univ Engn & Technol, Dept Comp Sci & Engn, Khulna 9203, Bangladesh

来源：

2020 IEEE REGION 10 SYMPOSIUM (TENSYMP) - TECHNOLOGY FOR IMPACTFUL SUSTAINABLE DEVELOPMENT | 2020年

关键词：

Fault Tolerance; Horizontal Parity; Vertical Parity; SuperQueen Parity; Mirror of SuperQueen Parity; Less Overhead; Higher Performance;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Erroneous data can cause a system to be failed. Though there are several methods for detection and correction, with the increasing amount of errors, it becomes difficult, for both detection, and correction of these erroneous codes. For solving these issues, this paper represents an effective method for solving multiple errors by using Horizontal-Vertical-SuperQueen (HVSQ) parity bits in code. It works with 121 data bits and 44 parity bits. And this method has a higher correction rate with less code overhead and higher code-rate. For these 121 bits of data, we need only 44 redundant bits which, indicate 36.36% of bit overhead and can solve up to 3 bit of errors. It also shows better accuracy in the increased number of errors in data bits.

引用

页码：1734 / 1737

页数：4

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