Peak power estimation of VLSI circuits: New peak power measures

被引：18
|
作者：
Hsiao, MS [1 ]
Rudnick, EM
Patel, JH
机构：
[1] Rutgers State Univ, Dept Elect & Comp Engn, Piscataway, NJ 08854 USA
[2] Univ Illinois, Ctr Reliable & High Performance Comp, Urbana, IL 61801 USA
来源：
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2000年 / 8卷 / 04期
关键词：
delay models; peak power; power consumption; power estimation; VLSI design;
D O I：
10.1109/92.863624
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
New measures of peak power are proposed in the context of sequential circuits, and an efficient automatic procedure is presented to obtain very good loser bounds on these measures, as well as providing the actual input vectors that attain such bounds. Automatic generation of a functional vector loop for near-worst case power consumption is also attained. Experiments show that vector sequences generated give much more accurate estimates of peak power dissipation and are generated in significantly shorter execution times than estimates made from randomly generated sequences for four delay models.
引用
收藏
页码：435 / 439
页数：5
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