共 17 条
- [2] Numerical study of gold wire bonding process on Cu/Low-k structures [J]. IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2007, 30 (03): : 448 - 456
- [5] Evaluation of Back End of Line Structures Underneath Wirebond Pads in Ultra Low-k Device [J]. 2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2012, : 1097 - 1102
- [6] Experimental and Numerical Investigations on Cu/low-k Interconnect Reliability during Copper Pillar Shear Test [J]. 2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2015, : 1594 - 1598
- [7] Numerical analysis by 3D finite element wire bond simulation on Cu/low-K structures [J]. PROCEEDINGS OF THE 7TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS. 1 AND 2, 2005, : 215 - 220
- [8] Degradation in TDDB of Cu/Low-k Test Structures Due to Field Interaction Between Adjacent Metal Lines [J]. 2013 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2013,
- [10] Study on Vertical TDDB Degradation Mechanism and its Relation to Lateral TDDB in Cu/Low-k Damascene Structures [J]. 2014 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2014,