Evaluation of Back End of Line Structures Underneath Wirebond Pads in Ultra Low-k Device

被引:0
|
作者
Aoki, Toyohiro [1 ]
Hisada, Takashi [1 ]
Okamoto, Keishi [2 ]
Malinowski, John C. [3 ]
Beckham, Keith F. [4 ]
Yang, Yong-Seok [5 ]
Kim, Joon-Su [5 ]
Harada, Shinichi [1 ,6 ]
机构
[1] IBM Japan Ltd, Yamato Lab, 1623-14 Shimotsuruma, Yamato, Kanagawa 2428502, Japan
[2] IBM Japan Ltd, Res Tokyo, Yamato, Kanagawa 2428502, Japan
[3] IBM Syst & Technol Grp, Essex Jct, VT 05452 USA
[4] IBM Syst & Technol Grp, Hopewell Jct, NY 12533 USA
[5] Amkor Technol Inc, Sungdong Ku, Seoul 133706, South Korea
[6] IBM Japan Ltd, Yamato Lab, Kanagawa Ku, Yokohama, Kanagawa 2210022, Japan
关键词
CMOS TECHNOLOGY;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Mechanical integrity of back end of line structures underneath wirebond pads was evaluated using 32 nm ultra low-k device by wire pull testing and 3D finite element analysis. Pad tearout rate at wire pull testing was measured for various Cu line/via structures. One key factor for robust bond pads is effective modulus in ULK levels. In addition, increased via and wiring metal density reduces the risk of pad tearout. For the evaluated structures in this work, a calculated effective modulus in ULK was a better index than metal layout type for assessment of bond pad robustness in cooperation with finite element analysis data. Wirebonding is another key factor affecting pad tearout. In this work, effects of wirebond geometry (i.e. wire size and bond ball size) on pad tearout were focused rather than the effect of parameter itself. With the robust BEOL stack and appropriate wirebonding conditions, module level reliability of 35 mu m ultra fine pitch wirebond on ultra low-k chip with circuit underneath bond pads was also demonstrated with a PBGA package.
引用
收藏
页码:1097 / 1102
页数:6
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