A flip chip packaged limiting amplifier with data rate of 10 Gb/s

被引:0
|
作者
Ju, CW [1 ]
Pack, KH
Lee, HT
Hyun, YC
机构
[1] Elect & Telecommun Res Inst, Basic Res Lab, Wireless Commun Devices Dept, Taejon 305350, South Korea
[2] Chungbuk Natl Univ, Dept Elect Engn, Chungju 561756, South Korea
关键词
flip chip; wafer level package; limiting amplifier;
D O I
暂无
中图分类号
O4 [物理学];
学科分类号
0702 ;
摘要
A 10 Gb/s limiting amplifier IC with the emitter area of 1.5 x 10 mum(2) for optical transmission system was designed and fabricated with a AlGaAs/GaAs HBTs technology. In this study, we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. To study the effect of WL-CSP, electricial performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the rise/fall times were about 90 ps, and the out put voltage swing was limited to 650 mV(p-p) with input voltage ranging from 50 to 500 mV. The Small signal gains in wafer and package module were 11.2 dB and 11.4 dB at 10 GHz respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.2 dB up to 10 GHz. But, the characteristics of return loss were improved in the package module. This is due to the short interconnection length by WL-CSP. In this study, we developed fine pitch bump with the 40 mum diameter and 100 mum pitch using the WL-CSP process. So, the WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.
引用
收藏
页码:S574 / S578
页数:5
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