Challenges in Delay Testing of Integrated Circuits

被引：0

作者：

Walker, D. M. H. ^{[1
]}

机构：

[1] Texas A&M Univ, Dept Comp Sci & Engn, College Stn, TX 77843 USA

来源：

IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE VLSI SYSTEMS, PROCEEDINGS | 2009年

关键词：

D O I：

10.1109/DFT.2009.53

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Delay testing of integrated circuits is increasingly focused on detecting small delay defects, and improving correlation to functional test. In this talk we will describe our recent efforts and results on industrial designs.

引用

页码：81 / 82

页数：2

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