Interface architecture generation for IP integration in SoC design

Designing component-based SoC (System On Chip) has become a communication design problem. The reuse of Intellectual Property (IP) cores in Multiprocessor SoC is facilitated by the concept of packaging and wrapping. In this paper, we present an approach to automate the integration process of hardware accelerators/coprocessors. This approach gives an interface modelling considering communication adaptation concepts/context throughout the integration steps. Graph formalism has been established to specify the interface considering the IP execution cycle accurate behaviour. This allows for automatic generation of interface architecture for simulation towards its synthesis. We illustrate the utility of the proposed framework that enables faster simulation times compared to existing methodologies which allow the designer to quickly evaluate alternative system implementations.