Delay-optimized realization of 2-parallel delayed LMS adaptive FIR filter

Motivated by improvement of convergence characteristics and throughput, this work develops a delay-optimized VLSI realization of the adaptive filter based on the 2-parallel delayed LMS (PDLMS) algorithm. The proposed design uses a novel parallel FIR filter structure based on the fast FIR algorithm. The throughput of the proposed architecture is not only two times that of the traditional structure at the same frequency, but also the convergence characteristic is close to that of the LMS algorithm. The fine-grained dot-product unit, fine-grained fused multiply-add unit and multiple-input-addition unit are adopted to reduce the latency of critical path. From the ASIC synthesis results we find that the proposed architecture of an 8-tap filter has nearly 25% less power and nearly 24% less area-delay-product ( ADP) than the best existing structure.