Demo: Overlay Architectures For Heterogeneous FPGA Cluster Management

被引:0
|
作者
Bollengier, Theotime [1 ]
Najem, Mohamad [2 ]
Le Lann, Jean-Christophe [2 ]
Lagadec, Loic [2 ]
机构
[1] B Com, Brest, France
[2] ENSTA Bretagne, Lab STICC MOCS, Brest, France
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Overlays are reconfigurable architectures synthesized on commercial of the shelf (COTS) FPGAs. Overlays bring some advantages such as portability, resources abstraction, fast configuration, and can exhibit features independent from the host FPGA. We designed a fine-grained overlay implementing novel features easing the management of such architectures in a cluster of heterogeneous COTS FPGAs. This demonstration shows the use of this overlay in an FPGA cluster, performing a hardware application live migration between two nodes of a cluster. It also illustrates fault tolerance of the cluster.
引用
收藏
页码:239 / 240
页数:2
相关论文
共 50 条
  • [41] High-Performance, Cost-Effective Heterogeneous 3D FPGA Architectures
    Le, Roto
    Reda, Sherief
    Bahar, R. Iris
    GLSVLSI 2009: PROCEEDINGS OF THE 2009 GREAT LAKES SYMPOSIUM ON VLSI, 2009, : 251 - 256
  • [42] A Survey on FPGA-Based Heterogeneous Clusters Architectures (vol 11, pg 67679, 2023)
    Samayoa, Werner Florian
    Crespo, Maria Liz
    Cicuttin, Andres
    Carrato, Sergio
    IEEE ACCESS, 2023, 11 : 129320 - 129320
  • [43] Parallel patterns for heterogeneous CPU/GPU architectures: Structured parallelism from cluster to cloud
    Campa, Sonia
    Danelutto, Marco
    Goli, Mehdi
    Gonzalez-Velez, Horacio
    Popescu, Alina Madalina
    Torquati, Massimo
    FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE, 2014, 37 : 354 - 366
  • [44] List scheduling: extension for contention awareness and evaluation of node priorities for heterogeneous cluster architectures
    Sinnen, O
    Sousa, L
    PARALLEL COMPUTING, 2004, 30 (01) : 81 - 101
  • [45] FPGA and CPLD architectures: A tutorial
    Brown, S
    Rose, J
    IEEE DESIGN & TEST OF COMPUTERS, 1996, 13 (02): : 42 - 57
  • [46] Exploration Environment for 3D Heterogeneous Tree-based FPGA Architectures (3D HT-FPGA)
    Pangracious, Vinod
    Mehrez, Habib
    Beltaief, Nizar
    Marrakchi, Zied
    Farooq, Umer
    2013 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG), 2013,
  • [47] Toward Operating System Assisted Hierarchical Memory Management for Heterogeneous Architectures
    Gerofi, Balazs
    Hori, Atsushi
    Shimada, Akio
    Ishikawa, Yutaka
    2012 SC COMPANION: HIGH PERFORMANCE COMPUTING, NETWORKING, STORAGE AND ANALYSIS (SCC), 2012, : 1351 - 1352
  • [48] DeSC: Decoupled Supply-Compute Communication Management for Heterogeneous Architectures
    Ham, Tae Jun
    Aragon, Juan L.
    Martonosi, Margaret
    PROCEEDINGS OF THE 48TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO-48), 2015, : 191 - 203
  • [49] Toward Operating System Assisted Hierarchical Memory Management for Heterogeneous Architectures
    Gerofi, Balazs
    Shimada, Akio
    Hori, Atsushi
    Ishikawa, Yutaka
    2012 SC COMPANION: HIGH PERFORMANCE COMPUTING, NETWORKING, STORAGE AND ANALYSIS (SCC), 2012, : 1350 - 1350