Threshold Gate-Based Circuits From Nanomagnetic Logic

被引：12

作者：

Papp, Adam ^{[1
]}

Niemier, Michael T. ^{[1
]}

Csurgay, Arpad ^{[2
]}

Becherer, Markus ^{[3
]}

Breitkreutz, Stephan ^{[3
]}

Kiermaier, Josef ^{[3
]}

Eichwald, Irina ^{[3
]}

Hu, X. Sharon ^{[1
]}

Ju, Xueming ^{[4
]}

Porod, Wolfgang ^{[1
]}

Csaba, Gyoergy ^{[1
]}

机构：

[1] Univ Notre Dame, Ctr Nano Sci & Technol, Notre Dame, IN 46556 USA

[2] Pazmany Peter Catholic Univ, Fac Informat Technol, H-1088 Budapest, Hungary

[3] Tech Univ Munich, Inst Tech Elect, D-80333 Munich, Germany

[4] Tech Univ Munich, Inst Nanoelect, D-80333 Munich, Germany

来源：

IEEE TRANSACTIONS ON NANOTECHNOLOGY | 2014年 / 13卷 / 05期

基金：

美国国家科学基金会;

关键词：

Co/Pt multilayers; majority logic; nanomagnetic logic (NML); threshold gate; FULL ADDER;

D O I：

10.1109/TNANO.2014.2342659

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper demonstrates the design of nanomagnetic logic (NML) gates with multiple weighted inputs, which are magnetic equivalents of threshold logic gates (TLGs). We use micromagnetic simulations to show that NML TLGs can be constructed with minimum overhead compared to standard NML gates, and they significantly reduce device footprint and interconnection complexity of magnetic logic circuits. As an example, we design a full adder circuit using said TLGs and compare its performance to majority-gate-based NML.

引用

页码：990 / 996

页数：7

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