A CMOS Micro-power, Class-AB "Flipped" Voltage Follower using the quasi floating-gate technique

被引：1
|
作者：
Ocampo-Hidalgo, J. J. [1 ]
Vazquez-Alvarez, I. [1 ]
Sandoval-Perez, S. [2 ]
Garcia-Lozano, R. Z. [3 ]
Gurrola, M. A. [4 ]
Molinar-Solis, J. E. [2 ]
机构：
[1] Univ Autonoma Metropolitana Azcapotzalco, Mexico City, DF, Mexico
[2] Inst Tecnol Cd Guzman, Cd Guzman, Jalisco, Mexico
[3] Univ Autonoma Estado Mexico, Toluca De Lerdo, Mex, Mexico
[4] Univ Guadalajara, Guadalajara, Jalisco, Mexico
来源：
INGENIERIA E INVESTIGACION | 2017年 / 37卷 / 02期
关键词：
CMOS analog integrated circuit design; quasi-floating gate circuits; low voltage; micro-power;
D O I：
10.15446/ing.investig.v37n2.62625
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
This paper presents the design and characterization of a new analog voltage follower for low-voltage applications. The main idea is based on the "Flipped" Voltage Follower and the use of the quasi-floating gate technique for achieving class AB operation. A test cell was simulated and fabricated using a 0,5 mu m CMOS technology. When the proposed circuit is supplied with VDD = 1,5 V, it presents a power consumption of only 413 mu W. Measurement and experimental results show a gain-bandwidth product of 10 MHz and a total harmonic distortion of 1,12 % at 1 MHz.
引用
收藏
页码：82 / 88
页数：7
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