A dynamic scaling FFT processor for DVB-T applications

被引：82
|
作者：
Lin, YW [1 ]
Liu, HY [1 ]
Lee, CY [1 ]
机构：
[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2004年 / 39卷 / 11期
关键词：
DVB-T; fast Fourier transform (FFT); orthogonal frequency division multiplexing (OFDM);
D O I：
10.1109/JSSC.2004.835815
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents an 8192-point FFT processor for DVB-T systems, in which a three-step radix-8 FFT algorithm, a new dynamic scaling approach, and a novel matrix prefetch buffer 1 are exploited. About 64 K bit memory space can be saved in the 8 K point FFT by the proposed dynamic scaling approach. Moreover, with data scheduling and pre-fetched buffering, single-port memory can be adopted without degrading throughput rate. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18-mum single-poly six-metal CMOS process with core area of 4.84 mm(2). Power dissipation is about 25.2 mW at 20 MHz.
引用
收藏
页码：2005 / 2013
页数：9
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