An FFT core for DVB-T/DVB-H receivers

被引：0

作者：

Cortes, A. ^{[1
]}

Sevillano, J. F. ^{[1
]}

Velez, I. ^{[1
]}

Irizar, A. ^{[1
]}

机构：

[1] CEIT, Dept Elect & Commun, San Sebastian, Spain

来源：

2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3 | 2006年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the design and implementation of a pipeline radix-2(2) SDF FFT core for DV-B-T/DVB-H receivers. DVB-T/DVB-H operation needs 2K/4K/8K multiple mode FFT processors. The necessary changes are introduced in the radix-2(2) SDF architecture to achieve an efficient FFT implementation. SNR and area results for different data and twiddle factor bitwidths are provided.

引用

页码：102 / 105

页数：4

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