An FFT Core for DVB-T/DVB-H Receivers

被引：8
|
作者：
Cortes, A. [1 ]
Velez, I.
Zalbide, I.
Irizar, A.
Sevillano, J. F.
机构：
[1] Univ Navarra, CEIT, Dept Elect & Commun, Donostia San Sebastian 20018, Spain
来源：
VLSI DESIGN | 2008年
关键词：
VLSI circuits;
D O I：
10.1155/2008/610420
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents the design and implementation of a 2K/4K/8K multiple mode FFT core for DVB-TIDVB-H receivers. The proposed core is based on a pipeline radix-2(2) SDF architecture. The necessary changes in the radix-2(2) SDF architecture to achieve an efficient FFT implementation are detailed. Quantization effects and tuning design parameters are analyzed for DVB-T/DVB-H. Area and power results are provided for the proposed core. Copyright (C) 2008 A. Cortes et al.
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页数：9
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