Low Loss and Low EMI Noise CSTBT With Split Gate and Recessed Emitter Trench

A novel carrier stored trench bipolar transistor (CSTBT) with split gate (SG) and recessed emitter trench (SGRET CSTBT) is proposed. The proposed device features a SG structure with thicker oxide layer under the trench gate and recessed trench emitter, respectively. Compared with the conventional CSTBT with recessed emitter trench (RET CSTBT), the proposed device not only significantly reduces the gate-collector capacitance (C-GC) but also alleviates the negative impact of the heavily doped n-type carrier stored layer on the breakdown voltage (BV). Simulation results show that with the similar BV of about 650V, the on-state voltage drop (V-ceon) at J(ce) =200A/cm(2) for the proposed SGRET CSTBT is only 1.11V, which is 0.19V lower than that of the conventional RET CSTBT. Moreover, compared with the conventional RET CSTBT, theC(GC)at the V-ce of 25V, total gate charge (Q(G)) and miller plateau charge (Q(GC)) for the proposed device are reduced by 84.3%, 38.6% and 51.6%, respectively. As a result, the trade-off relationship between theV(ceon) and turn-off loss (E-off) as well as trade-off relationship between the turn-on loss (E-on) and dV(ak)/dt of the free-wheeling diode (FWD) are significantly improved for the proposed device. At the sameV(ceon)of 1.16V, theE(off)is reduced from 9.2mJ/cm(2) of the conventional one to 3.3mJ/cm(2) of the proposed device. At the sameE(on)of 8.3mJ/cm(2), the dV(ak)/dt of FWD for the proposed device is reduced by 24.5% compared with that of the conventional RET CSTBT, which significantly suppresses the EMI noise.