A 10-Bit 120 kS/s SAR ADC Without Reset Energy for Biomedical Electronics

A 10-bit 120 kS/s successive-approximation-register analog-to-digital converter (SAR ADC) is realized for implantable multichannel neural recording system. In order to reduce power consumption and area occupation, an improved energy-efficient V-CM-based switching scheme is proposed. Different from the monotonic switching scheme, the switching procedure for each bit cycle of this proposed scheme is almost symmetrical, which facilitates the comparator design. Additionally, since all these capacitors are connected to V-CM in the sampling phase, the reset energy of this switching scheme is zero. Bootstrapped sampling switches are employed for linearity improvement. Realized in 0.18-mu m CMOS, the proposed ADC occupies an active area of 0.13 mm(2). Including the I/O and two 4-to-1 multiplexers, the power consumption is 2.97 mu W at 120 kS/s sampling rate. The figure-of-merit of this proposed SAR ADC is about 36.9 fJ/conversion-step.