Scaling limits of CMOS integrated circuits

被引：0
|
作者：
Dilger, M
机构：
来源：
NANOFAIR 2004 NEW IDEAS FOR INDUSTRY | 2004年 / 1839卷
关键词：
D O I：
暂无
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
引用
收藏
页码：17 / 23
页数：7
相关论文
共 50 条
  • [41] Nanostructured electrodes for biocompatible CMOS integrated circuits
    Graham, Anthony H. D.
    Bowen, Chris R.
    Robbins, Jon
    Lalev, Georgi
    Marken, Frank
    Taylor, John
    SENSORS AND ACTUATORS B-CHEMICAL, 2010, 147 (02): : 697 - 706
  • [42] CMOS INTEGRATED-CIRCUITS FOR MULTIVALUED LOGIC
    MOUFTAH, HT
    SMITH, KC
    INTERNATIONAL JOURNAL OF ELECTRONICS, 1985, 58 (01) : 43 - 50
  • [43] CMOS Integrated Circuits for the Quantum Information Sciences
    Anders J.
    Babaie M.
    Bardin J.C.
    Bashir I.
    Billiot G.
    Blokhina E.
    Bonen S.
    Charbon E.
    Chiaverini J.
    Chuang I.L.
    Degenhardt C.
    Englund D.
    Geck L.
    Le Guevel L.
    Ham D.
    Han R.
    Ibrahim M.I.
    Kruger D.
    Lei K.M.
    Morel A.
    Nielinger D.
    Pillonnet G.
    Sage J.M.
    Sebastiano F.
    Staszewski R.B.
    Stuart J.
    Vladimirescu A.
    Vliex P.
    Voinigescu S.P.
    IEEE Transactions on Quantum Engineering, 2023, 4
  • [44] RELIABILITY OF CMOS SOS INTEGRATED-CIRCUITS
    VELORIC, H
    DUGAN, MP
    MORRIS, W
    DENNING, R
    SCHNABLE, G
    RCA REVIEW, 1984, 45 (02): : 230 - 248
  • [45] A Voltage Scaling Model for Performance Evaluation in Digital CMOS Circuits
    von Arnim, Klaus
    Schruefer, Klaus
    Baumann, Thomas
    Hofmann, Karl
    Schulz, Thomas
    Pacha, Christian
    Berthold, Joerg
    2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, 2009, : 467 - 470
  • [46] The impact of scaling down to deep submicron on CMOS RF circuits
    Huang, QT
    Piazza, F
    Orsatti, P
    Ohguro, T
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (07) : 1023 - 1036
  • [47] Demonstration of Ge Nanowire CMOS Devices and Circuits for Ultimate Scaling
    Wu, Heng
    Wu, Wangran
    Si, Mengwei
    Ye, Peide D.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (08) : 3049 - 3057
  • [48] Transistor Sizing and VDD Scaling for Low Power CMOS Circuits
    Kabbani, Adnan
    2009 JOINT IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS AND TAISA CONFERENCE, 2009, : 93 - 96
  • [49] CMOS SRAM Scaling Limits under Optimum Stability Constraints
    Makosiej, Adam
    Thomas, Olivier
    Amara, Amara
    Vladimirescu, Andrei
    2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2013, : 1460 - 1463
  • [50] Development of 0.50μm CMOS Integrated Circuits Technology
    Yu Shan
    Chinese Journal of Systems Engineering and Electronics, 1992, (04) : 7 - 10
12345