共 50 条
- [1] Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADC 2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2009, : 291 - +
- [2] Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2010, 26 (01): : 59 - 71
- [3] Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study Journal of Electronic Testing, 2010, 26 : 59 - 71
- [4] Signature-Based Testing for Adaptive Digitally-Calibrated Pipelined Analog-to-Digital Converters 2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2009, : 597 - +
- [6] A linear-approximation technique for digitally-calibrated pipelined A/D converters 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 1382 - 1385
- [8] A Digitally-Calibrated 10GS/s Reconfigurable Flash ADC in 65-nm CMOS 2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2013, : 2444 - 2447
- [9] A 950μW 5.5-GHz Low Voltage PLL with Digitally-Calibrated ILFD and Linearized Varactor 2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2014, : 23 - 24
- [10] A 10-Bit 200-MS/s Digitally-Calibrated Pipelined ADC Using Switching Opamps 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012, : 1042 - 1045