Applying decay to reduce dynamic power in set-associative caches

被引:0
|
作者
Keramidas, Georgios [1 ]
Xekalakis, Polychronis [2 ]
Kaxiras, Stefanos [1 ]
机构
[1] Univ Patras, Dept Elect & Comp Engn, GR-26110 Patras, Greece
[2] Univ Edinburgh, Dept Informat, Edinburgh EH8 9YL, Midlothian, Scotland
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
\In this paper, we propose a, novel approach to reduce dynamic power in set-associative caches that leverages on a leakage-saving proposal, namely Cache Decay. We thus open the possibility to unify dynamic and leakage management in the same framework. The main intuition is that in a decaying cache, dead lines in a set need not be searched. Thus, rather than trying to predict which cache way holds a specific line, we predict, for each way, whether the line could be live in it. We access all the ways that possibly contain the live line and we call this way-selection. In contrast to way-prediction, way-selection cannot be wrong: the line is either in the selected ways or not in the cache. The important implication is that we have a fixed hit time -- indispensable for both performance and ease-of-implementation reasons. In order to achieve high accuracy, in terms of total ways accessed, we use Decaying Bloom filters to track only the live lines in ways - dead lines are automatically purged. We offer efficient implementations of such autonomously Decaying Bloom filters, using novel quasi-static cells. Our prediction approach grants us high-accuracy in narrowing the choice of ways for hits as well as the ability to predict misses - a known weakness of way-prediction.
引用
收藏
页码:38 / +
页数:3
相关论文
共 50 条
  • [31] Dynamic Associative Caches: Reducing Dynamic Energy of First Level Caches
    Dayalan, Karthikeyan
    Ozsoy, Meltem
    Ponomarev, Dmitry
    [J]. 2014 32ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 2014, : 271 - 277
  • [32] Design of an adjustable-way set-associative cache
    Chen, HC
    Chiang, JS
    [J]. 2001 IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS AND SIGNAL PROCESSING, VOLS I AND II, CONFERENCE PROCEEDINGS, 2001, : 315 - 318
  • [33] Improved Procedure Placement for Set Associative Caches
    Liang, Yun
    Mitra, Tulika
    [J]. PROCEEDINGS OF THE 2010 INTERNATIONAL CONFERENCE ON COMPILERS, ARCHITECTURES AND SYNTHESIS FOR EMBEDDED SYSTEMS (CASES '10), 2010, : 147 - 156
  • [34] Partial Tag Comparison: A new technology for power-efficient set-associative cache designs
    Min, R
    Xu, ZY
    Hu, YM
    Jone, WB
    [J]. 17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: DESIGN METHODOLOGIES FOR THE GIGASCALE ERA, 2004, : 183 - 188
  • [35] Reducing Dynamic Energy of Set-Associative L1 Instruction Cache by Early Tag Lookup
    Zhang, Wei
    Zhang, Hang
    Lach, John
    [J]. 2015 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED), 2015, : 49 - 54
  • [36] An improved approach for set-associative instruction cache partial analysis
    Ballabriga, C.
    Casse, H.
    Sainrat, F.
    [J]. APPLIED COMPUTING 2008, VOLS 1-3, 2008, : 360 - 367
  • [37] SET-ASSOCIATIVE CACHE SIMULATION USING GENERALIZED BINOMIAL TREES
    SUGUMAR, RA
    ABRAHAM, SG
    [J]. ACM TRANSACTIONS ON COMPUTER SYSTEMS, 1995, 13 (01): : 32 - 56
  • [38] A low energy set-associative I-Cache with extended BTB
    Inoue, K
    Moshnyaga, VG
    Murakami, K
    [J]. ICCD'2002: IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 2002, : 187 - 192
  • [39] IPStash: A set-associative memory approach for efficient IP-lookup
    Kaxiras, S
    Keramidas, G
    [J]. IEEE INFOCOM 2005: THE CONFERENCE ON COMPUTER COMMUNICATIONS, VOLS 1-4, PROCEEDINGS, 2005, : 992 - 1001
  • [40] Scope-Aware Useful Cache Block Calculation for Cache-Related Pre-Emption Delay Analysis With Set-Associative Data Caches
    Zhang, Wei
    Guan, Nan
    Ju, Lei
    Tang, Yue
    Liu, Weichen
    Jia, Zhiping
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 39 (10) : 2333 - 2346