共 50 条
- [1] Dynamic co-allocation of level one caches [J]. EMBEDDED SOFTWARE AND SYSTEMS, PROCEEDINGS, 2005, 3820 : 373 - 385
- [2] Applying decay to reduce dynamic power in set-associative caches [J]. HIGH PERFORMANCE EMBEDDED ARCHITECTURES AND COMPILERS, PROCEEDINGS, 2007, 4367 : 38 - +
- [3] Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches [J]. TRANSACTIONS ON HIGH-PERFORMANCE EMBEDDED ARCHITECTURES AND COMPILERS II, 2009, 5470 : 4 - 22
- [5] Timing analysis for data caches and set-associative caches [J]. THIRD IEEE REAL-TIME TECHNOLOGY AND APPLICATIONS SYMPOSIUM, PROCEEDINGS, 1997, : 192 - 202
- [6] Optimal management of dynamic buffer caches [J]. PERFORMANCE EVALUATION, 1996, 26 (04) : 239 - 262
- [7] Low energy associative data caches for embedded systems [J]. EMBEDDED SOFTWARE FOR SOC, 2003, : 513 - 525
- [8] Reactive-associative caches [J]. 2001 INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PROCEEDINGS, 2001, : 49 - 60
- [9] The Case for Associative DRAM Caches [J]. MEMSYS 2016: PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON MEMORY SYSTEMS, 2016, : 211 - 219
- [10] PAGE ASSOCIATIVE CACHES ON FUTUREBUS [J]. MICROPROCESSORS AND MICROSYSTEMS, 1988, 12 (03) : 159 - 163