Development of High Performance Hardware by High-Level Synthesis of Median-Based Dynamic Background Subtraction Method with Multiple Line Buffers

被引：0

作者：

Shinyamada, Kohei ^{[1
]}

Yamawaki, Akira ^{[1
]}

机构：

[1] Kyushu Inst Technol, Dept Engn, Kitakyushu, Fukuoka, Japan

来源：

2021 IEEE REGION 10 CONFERENCE (TENCON 2021) | 2021年

关键词：

FPGA; Image Processing; HLS;

D O I：

10.1109/TENCON54134.2021.9707206

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Hardware processing is suitable for embedded image processing systems because of its lower power consumption and higher performance compared to software processing. To facilitate development, a tool called high-level synthesis, which automatically converts high-level languages into hardware description languages, is used. However, high-level synthesis of pure software does not necessarily generate efficient hardware. In this study, we attempted to generate high-performance image processing hardware using a median-based dynamic background subtraction method. As a result, we found that high-performance hardware can be generated when multiple line buffers are introduced. Compared to the non-introduced one, the performance was improved by about 13 times.

引用

页码：123 / 127

页数：5

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