A Generic Procedural Generator for Sizing of Analog Integrated Circuits

被引：0

作者：

Schweikardt, Matthias ^{[1
]}

Uhlmann, Yannick ^{[1
]}

Leber, Florian ^{[1
]}

Scheible, Juergen ^{[1
]}

Habal, Husni ^{[2
]}

机构：

[1] Reutlingen Univ, D-72762 Reutlingen, Germany

[2] Infineon Technol AG, D-85579 Neubiberg, Germany

来源：

2019 15TH CONFERENCE ON PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIME) | 2019年

关键词：

procedure; generator; expert design plan; electronic design automation; smart power ic; miller operational amplifier;

D O I：

10.1109/prime.2019.8787743

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we address the novel EDP (Expert Design Plan) principle for procedural design automation of analog integrated circuits, which captures the knowledge-based design strategy of human circuit designers in an executable script, making it reusable. We present the EDP Player, which enables the creation and execution of EDPs for arbitrary circuits in the Cadence (R) Virtuoso (R) Design Environment. The tool provides a generic version of an instruction set, called EDPL (EDP-Language), enabling emulation of a typical manual analog sizing flow. To automate the design of a Miller Operational Amplifier and to create variants of a Smart Power IC, several EDPs were implemented using this tool. Employing these EDPs leads to a strong reduction of design time without compromising design quality or reliability.

引用

页码：17 / 20

页数：4

共 50 条

[41] Parasitic-Aware GP-Based Many-Objective Sizing Methodology for Analog and RF Integrated Circuits
Liao, Tuotian
Zhang, Lihong
2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2017, : 475 - 480
[42] MOSFET ANALOG INTEGRATED CIRCUITS - 2.
Rehman, M.A.
Electronic Engineering (London), 1980, 52 (646): : 75 - 83
[43] Analog statistical simulation for bipolar integrated circuits
Rencher Mark
Analog Integrated Circuits and Signal Processing, 1991, 1 (02) : 157 - 164
[44] Hierarchical fault diagnosis of analog integrated circuits
Chung Kin Ho
Shepherd, P.R.
Eberhardt, F.
Tenten, W.
IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 2001, 48 (08): : 921 - 929
[45] Analog Integrated Circuits and Signal Processing: Foreword
Courtois, B.
Analog Integrated Circuits and Signal Processing, 2002, 32 (01)
[46] On synthesis of manufacturable and testable analog integrated circuits
Huang, WH
Resh, JA
Wey, CL
1998 MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, 1999, : 340 - 343
[47] Hierarchical fault diagnosis of analog integrated circuits
Ho, CK
Shepherd, PR
Eberhardt, F
Tenten, W
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2001, 48 (08) : 921 - 929
[48] Integrated Analogical Signs Generator for Testing Mixed Integrated Circuits
Simancas-Garcia, Jose L.
Melendez-Pertuz, Farid A.
Combita-Nino, Harold
Gonzalez, Ramon E. R.
Collazos-Morales, Carlos
INTELLIGENT HUMAN COMPUTER INTERACTION, IHCI 2021, 2022, 13184 : 483 - 495
[49] Efficient Parasitic-aware gm/ID-based Hybrid Sizing Methodology for Analog and RF Integrated Circuits
Liao, Tuotian
Zhang, Lihong
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2021, 26 (02)
[50] Calculation of Total Integrated Noise in Analog Circuits
Dastgheib, Alireza
Murmann, Boris
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2008, 55 (10) : 2988 - 2993

← 1 2 3 4 5 →