A Generic Procedural Generator for Sizing of Analog Integrated Circuits

被引：0

作者：

Schweikardt, Matthias ^{[1
]}

Uhlmann, Yannick ^{[1
]}

Leber, Florian ^{[1
]}

Scheible, Juergen ^{[1
]}

Habal, Husni ^{[2
]}

机构：

[1] Reutlingen Univ, D-72762 Reutlingen, Germany

[2] Infineon Technol AG, D-85579 Neubiberg, Germany

来源：

2019 15TH CONFERENCE ON PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIME) | 2019年

关键词：

procedure; generator; expert design plan; electronic design automation; smart power ic; miller operational amplifier;

D O I：

10.1109/prime.2019.8787743

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we address the novel EDP (Expert Design Plan) principle for procedural design automation of analog integrated circuits, which captures the knowledge-based design strategy of human circuit designers in an executable script, making it reusable. We present the EDP Player, which enables the creation and execution of EDPs for arbitrary circuits in the Cadence (R) Virtuoso (R) Design Environment. The tool provides a generic version of an instruction set, called EDPL (EDP-Language), enabling emulation of a typical manual analog sizing flow. To automate the design of a Miller Operational Amplifier and to create variants of a Smart Power IC, several EDPs were implemented using this tool. Employing these EDPs leads to a strong reduction of design time without compromising design quality or reliability.

引用

页码：17 / 20

页数：4

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