Impact of Process Variations on the Capacitance and Electrical Resistance down to 1.44 μm Hybrid Bonding Interconnects

被引:4
|
作者
Ayoub, B. [1 ,2 ]
Lhostis, S. [1 ]
Moreau, S. [3 ]
Perez, E. Leon [1 ]
Jourdon, J. [1 ]
Lamontagne, P. [1 ]
Deloffre, E. [1 ]
Mermoz, S. [1 ]
de Buttet, C. [3 ]
Balan, V [3 ]
Euvard, C. [3 ]
Exbrayat, Y. [3 ]
Fremont, H. [2 ]
机构
[1] STMicroelectronics, 850 Rue Jean Monnet, F-38926 Crolles, France
[2] Univ Bordeaux, IMS Lab, UMR 5218, F-33405 Talence, France
[3] Univ Grenoble Alpes, LETI, CEA, F-38000 Grenoble, France
关键词
D O I
10.1109/EPTC50525.2020.9315028
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
With the rising of Hybrid Bonding (HB) as an interesting solution for fine-pitch 3D integration, the influence of process induced variations on performances is a demanding and crucial task. A 3D stacked test vehicle with hybrid bonding pitch ranging from 6.8 down to 1.44 mu m was processed and analyzed. A deep analysis on the influence of process variations is conducted and correlated to electrical measurements thanks to a dedicated simulation methodology. This allows a better understating of the process variation parameters that affects electrical resistance and capacitance along with their relative importance which is essential for optimization. The common parameter affecting both capacitance and electrical resistance is Wafer-to-Wafer overlay between top and bottom wafers arising the need for high accuracy in bonding alignment. The quality of the hybrid bonding interface is discussed thanks to the simulation model, before and after robustness tests depending on hybrid bonding pitch, leading to an estimation of contact resistivity around 2.10(-10) Omega.cm(2) for the 1.44 mu m-pitch structure.
引用
收藏
页码:453 / 458
页数:6
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