Simulation and analysis of inductive impact on VLSI interconnects in the presence of process variations

被引：0

作者：

Qi, XN ^{[1
]}

Lo, SC ^{[1
]}

Luo, YS ^{[1
]}

Gyure, A ^{[1
]}

Shahram, M ^{[1
]}

Singhal, K ^{[1
]}

机构：

[1] Synopsys Inc, Mountain View, CA 94043 USA

来源：

CICC: PROCEEDINGS OF THE IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2005年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

On-chip inductance impact on signal integrity, complicated by process variations, becomes challenging for global interconnects in nanometer designs. Simulation and analysis of on-chip buses are presented for the impact of inductance in the presence of process variations. Results show that in 90nm technology there is significant inductive impact on max-timing (similar to 9% push-out vs. RC delay) and noise (similar to 2x RC noise). Device and interconnect variations add similar to 4% into RLC max-timing impact, while their impact on RLC signal noise is non-appreciable.

引用

页码：309 / 312

页数：4

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