The effect of fluorine in an advanced CMOS process with triple (1.6/2.2/5.2nm) nitrided gate oxide

被引:3
|
作者
Hook, TB [1 ]
Kontra, R [1 ]
Burnham, J [1 ]
Lavoie, M [1 ]
机构
[1] IBM Corp, Microelec, Essex Jct, VT 05452 USA
来源
2003 8TH INTERNATIONAL SYMPOSIUM ON PLASMA- AND PROCESS-INDUCED DAMAGE | 2003年
关键词
D O I
10.1109/PPID.2003.1200945
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Fluorine is introduced into the pfet and nfet of a triple-oxide (1.6/2.2/5.2nm) 90nm nitrided-oxide CMOS technology. While the effects on the pfet gate oxide are relatively subtle, the nfet is very significantly affected. The effective thickness of the oxide increases by 0.5nm, much of the nitrogen is removed, and the structural integrity of the film is compromised. Electrical data, SIMS, TEM, and HRTEM analysis are used to characterize the films.
引用
收藏
页码:150 / 153
页数:4
相关论文
共 37 条
  • [31] Analysis of USJ formation with combined RTA/laser annealing conditions for 28 nm high-k/metal gate CMOS technology using advanced TCAD for process and device simulation
    Bazizi, E. M.
    Zaka, A.
    Benistant, F.
    SOLID-STATE ELECTRONICS, 2013, 83 : 61 - 65
  • [32] An Extended-Gate Field-Effect Transistor Applied to Resistive Divider Integrated With the Readout Circuit Using 180nm CMOS Process for Uric Acid Detection
    Kuo, Po-Yu
    Chen, Yung-Yu
    Lai, Wei-Hao
    Chang, Chun-Hung
    IEEE SENSORS JOURNAL, 2021, 21 (18) : 20229 - 20238
  • [33] A Dual Core Oxide 8T SRAM Cell with Low Vccmin and Dual Voltage Supplies in 45nm Triple Gate Oxide and Multi Vt CMOS for Very High Performance yet Low Leakage Mobile SoC Applications
    Liu, Ping
    Wang, Joseph
    Phan, Michael
    Garg, Manish
    Zhang, Ron
    Cassier, Amer
    Chua-Eoan, Lew
    Andreev, Boris
    Weyland, Sebastien
    Ekbote, Shashank
    Han, Michael
    Fischer, Jeff
    Yeap, Geoffrey C-F
    Wang, Ping-Wei
    Li, Quincy
    Hou, C. S.
    Lee, S. B.
    Wang, Y. F.
    Lin, S. S.
    Cao, M.
    Mii, Y. J.
    2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2010, : 135 - +
  • [34] Low damage fully self-aligned replacement gate process for fabricating deep sub-100 nm gate length GaAs metal-oxide-semiconductor field-effect transistors
    Li, X.
    Bentley, S.
    McLelland, H.
    Holland, M. C.
    Zhou, H.
    Thoms, S.
    Macintyre, D. S.
    Thayne, I. G.
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2010, 28 (06): : C6L1 - C6L5
  • [35] Fully self-aligned process for fabricating 100 nm gate length enhancement mode GaAs metal-oxide-semiconductor field-effect transistors
    Li, Xu
    Hill, Richard J. W.
    Longo, Paolo
    Holland, Martin C.
    Zhou, Haiping
    Thoms, Stephen
    Macintyre, Douglas S.
    Thayne, Iain G.
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2009, 27 (06): : 3153 - 3157
  • [36] A low damage etching process of sub-100nm platinum gate line for iii-v metal-oxide-semiconductor field-effect transistor fabrication and the optical emission spectrometry of the inductively coupled plasma of sf 6/c4f8
    Li, Xu
    Zhou, Haiping
    Hilly, Richard J. W.
    Holland, Martin
    Thayne, Iain G.
    Japanese Journal of Applied Physics, 2012, 51 (1 PART 2):
  • [37] A Low Damage Etching Process of Sub-100 nm Platinum Gate Line for III-V Metal-Oxide-Semiconductor Field-Effect Transistor Fabrication and the Optical Emission Spectrometry of the Inductively Coupled Plasma of SF6/C4F8
    Li, Xu
    Zhou, Haiping
    Hill, Richard J. W.
    Holland, Martin
    Thayne, Iain G.
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2012, 51 (01)