High voltage devices in advanced CMOS technologies

被引:24
|
作者
Bianchi, R. A. [1 ]
Raynaud, C. [1 ]
Blanchet, F. [1 ]
Monsieur, F. [1 ]
Noblanc, O. [1 ]
机构
[1] STMicroelectronics, F-38926 Crolles, France
来源
PROCEEDINGS OF THE IEEE 2009 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2009年
关键词
D O I
10.1109/CICC.2009.5280839
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
CMOS technologies for mobile systems require integrated high voltage devices to address analog baseband and RF power applications. Technology and device architecture evolution, from 0.5 mu m BCD-like to advanced 45nm CMOS, on bulk and thin SOI substrates, are reviewed in this paper. Main challenges encountered when integrating these devices in advanced CMOS are explained. The influence of the gate oxide thickness on the relevant figures of merit and some considerations on performance-reliability trade-off are provided.
引用
收藏
页码:363 / 369
页数:7
相关论文
共 50 条
  • [31] Strain mapping for advanced CMOS technologies
    Oezdoel, V. B.
    Tyutyunnikov, D.
    Koch, C. T.
    van Aken, P. A.
    CRYSTAL RESEARCH AND TECHNOLOGY, 2014, 49 (01) : 38 - 42
  • [32] Modeling of gain in advanced CMOS technologies
    Spessot, A.
    Gattel, F.
    Fantini, P.
    Marmiroli, A.
    NSTI NANOTECH 2008, VOL 3, TECHNICAL PROCEEDINGS, 2008, : 825 - 828
  • [33] Localized TDDB failures related to STI corner profile in advanced embedded high voltage CMOS technologies for power management units
    Chan, Yee Ming
    Moey, Chin Boon
    Kuan, Hing Poh
    ISSM 2007: 2007 INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, CONFERENCE PROCEEDINGS, 2007, : 487 - 490
  • [34] New Cost-Effective Integration Schemes Enabling Analog and High-Voltage Design in Advanced CMOS SOC Technologies
    Benaissa, K.
    Baldwin, G.
    Liu, S.
    Srinivasan, P.
    Hou, F.
    Obradovic, B.
    Yu, S.
    Yang, H.
    McMullan, R.
    Reddy, V.
    Chancellor, C.
    Venkataraman, S.
    Lu, H.
    Dey, S.
    Cirba, C.
    2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2010, : 221 - 222
  • [35] IMPROVED HCI OF EMBEDDED HIGH VOLTAGE EDNMOS IN ADVANCED CMOS PROCESS
    Liu, Junwen
    Chen, Hualun
    Chen, Yu
    2020 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2020 (CSTIC 2020), 2020,
  • [36] Over 2000 VFLR termination technologies for SiC high voltage devices
    Onose, H
    Oikawa, S
    Yatsuo, T
    Yutaka
    12TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS - PROCEEDINGS, 2000, : 245 - 248
  • [37] Monolithic voltage conversion in low-voltage CMOS technologies
    Kursun, V
    De, VK
    Friedman, EG
    Narendra, SG
    MICROELECTRONICS JOURNAL, 2005, 36 (09) : 863 - 867
  • [38] Design and Optimization of SCR Devices for On-chip ESD Protection in Advanced SOI CMOS Technologies
    Li, Junjun
    Di Sarro, James
    Gauthier, Robert
    2012 34TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD), 2012,
  • [39] ESD issues in advanced CMOS bulk and FinFET technologies: Processing, protection devices and circuit strategies
    Russ, Christian
    MICROELECTRONICS RELIABILITY, 2008, 48 (8-9) : 1403 - 1411
  • [40] Channel hot carrier effects in n-MOSFET devices of advanced submicron CMOS technologies
    La Rosa, Giuseppe
    Rauch, Stewart E., III
    MICROELECTRONICS RELIABILITY, 2007, 47 (4-5) : 552 - 558