Test, diagnosis and fault simulation of embedded RAM modules in SRAM-based FPGAs

被引：2
|
作者：
Niamat, M. Y.
Nemade, D. M.
Jamali, M. M.
机构：
[1] Univ Toledo, Program Comp Sci & Engn Technol, Toledo, OH 43606 USA
[2] Univ Toledo, Dept Elect Engn & Comp Sci, Toledo, OH 43606 USA
来源：
MICROELECTRONIC ENGINEERING | 2007年 / 84卷 / 02期
关键词：
FPGA; test; structural testing; March test; MATS plus; stuck at fault; fault diagnosis;
D O I：
10.1016/j.mee.2006.02.016
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a unique scheme for testing and locating multiple stuck at faults in the embedded RAM modules of SRAM-based FPGAs. The RAM modules are tested using the MATS++ algorithm. The interconnection scheme makes it possible to test all the cells within the RAM modules in the FPGA in just one test configuration. We also develop a diagnosis scheme capable of locating the faulty RAM cells and the CLB in which it is located. In this research, emphasis is also laid on reducing the testing time, which is achieved by partitioning the FPGA into two halves. (c) 2006 Elsevier B.V. All rights reserved.
引用
收藏
页码：194 / 203
页数：10
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