Scalable delta-sigma modulator readout architecture for array-based sensor system

A scalable and modular delta-sigma modulator readout architecture and an implementation for an array-based sensor system are presented. The proposed readout system has parallel finite impulse response (FIR) filters that are one-to-one mapped to a large-scale array of delta-sigma modulators. The proposed filter uses bit-serial arithmetic, and it provides simultaneous and continuous filtering and readout capability to double the effective sample rate with a single concurrent conversion and readout phase. The oversampling rate and the filter coefficients can be adjusted flexibly to the design needs, and the filter array size can be increased modularly with a minimal additional circuits. A prototype filter module with a 255-tap FIR filter shows maximum 95MSamples/sec in 0.18 mu m CMOS technology, and an array of 256 filter modules produces 377kFrames/sec. A filter module is about 145 mu m wide and 7.45 mu m high.