A MULTI-STANDARD VIDEO DECODER FOR HIGH DEFINITION VIDEO APPLICATIONS

被引：0

作者：

Chien, Cheng-An ^{[1
]}

Chien, Chih-Da ^{[1
]}

Chu, Jui-Chin ^{[1
]}

Guo, Jiun-In ^{[1
]}

Cheng, Ching-Hwa ^{[2
]}

机构：

[1] Natl Chung Cheng Univ, Dept CSIE, Chiayi, Taiwan

[2] Feng Chia Univ, Dept EE, Taichung, Taiwan

来源：

ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5 | 2009年

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Through reducing 70% of external memory bandwidth and 60% of computational complexity, the proposed 252 Kgates/71 mW/0.13um multi-standard (JPEG/MPEG-1/2/4/H.264) video decoder reduces 72% in gate count and 87% in power consumption as compared to the state-of-the-art design, when operating at 120MHz for real-time HD1080 video decoding with single AHB-based SDR memory.

引用

页码：1933 / 1933

页数：1

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